The present invention relates o a technique which is effective in the application thereof to a semiconductor integrated circuit device having a self-aligned bipolar transistor.
The bipolar transistor being developed by the present inventor is formed by SEPT (Selective Etching of Poly-silicon Technology). In the bipolar transistor which adopts this technology, a base lead-out electrode, an emitter opening, an emitter region and an emitter lead-out electrode can each be formed by self alignment with respect to a base region. In the bipolar transistor formed by this technology, it is not required to consider a mask alignment margin in the manufacturing process such as a base-emitter mask alignment margin, so the area occupied by the bipolar transistor can be reduced. As a result, the semiconductor integrated circuit device having this bipolar transistor can attain a high frequency characteristic or a high degree of integration.
In the aforesaid bipolar transistor it is considered that reducing the junction depth of the emitter region is important for attaining a high frequency characteristic or a high degree of integration. In the bipolar transistor being developed by the present invention, the junction depth of the emitter region is made shallow by the adoption of the following manufacturing process, which is not a known technique.
First, a polycrystalline silicon film serving as an emitter led-out electrode is deposited on a main surface of a p-type base region (an intrinsic base region) which is formed so as to be surrounded with a base lead-out electrode provided on a main surface of a semiconductor substrate. The polycrystalline silicon film is deposited throughout the whole surface of the semiconductor substrate by a CVD (Chemical Vapor Deposition) method at a film thickness of about 200 to about 250 nm. The polycrystalline silicon film is formed using a so-called non-doped polycrystalline silicon without introducing impurities which decrease the resistance value. The base lead-out electrode is formed by a polycrystalline silicon film deposited by the CVD method, with p-type impurity being introduced in the polycrystalline silicon film. On the surface of the polycrystalline silicon film base lead-out electrode, an insulating film (silicon oxide film) is formed for isolation by a thermal oxidation method. The size of the emitter opening for connection between the emitter lead-out electrode and the emitter region is defined substantially by the insulating film. This insulating film electrically isolates the base lead-out electrode and the emitter lead-out electrode from each other.
Next, an n-type impurity, e.g. As, is introduced into the polycrystalline silicon film (non-doped polycrystalline silicon). The n-type impurity is introduced in a sharp impurity atom concentration profile in order to enhance the controllability for the impurity concentration. Such sharp impurity atom concentration profile is obtained by an ion implantation method using 50-80 KeV energy. The As thus introduced under such conditions forms a peak of impurity concentration at a depth of about 50 nm from the surface of the polycrystalline silicon film.
Then, part of the n-type impurity introduced into the polycrystalline silicon film is diffused from the polycrystalline silicon film to the main surface portion of the p-type base region (the main surface of the single crystal silicon substrate) by a drive-in diffusion method using heat treatment, to form an n-type emitter region. By utilizing the drive-in diffusion method, the junction depth of the n-type emitter region can be made smaller than in a direct ion-implantation method, due to the lower temperature required for drive-in diffusion, and also to the absence of damage treatment needed for such problems as crystal defects of the surface of the single crystal silicon substrate. The n-type impurity remaining in the aforementioned polycrystalline silicon film is formed as an emitter lead-out electrode.
The bipolar transistor using such a polycrystalline silicon film for both the base lead-out electrode and the emitter lead-out electrode is also called a double-polySi-self-aligned bipolar transistor, which permits attenuation of an active region thereof, shallow junction and, thus, high speed. Such a bipolar transistor having a double-polySi structure is described, for example, in "Nikkei Microdevices", November 1985 number, pp. 67-78.
During development of a bipolar transistor formed by the foregoing SEPT method, the present inventors discovered the following problem. This problem will be explained below with reference to FIG. 25.
FIG. 25 illustrates a bipolar transistor Bip formed on a main surface of a semiconductor substrate 1 having an n-type collector region 3, a p-type base region 11 and an n-type emitter region 17. Around the p-type base region 11 there is formed a p-type external base region 10, on which is provided and electrically connected a base lead-out electrode 9 formed by a polycrystalline silicon film. Contacting and extending sideways of the external base region 10 in FIG. 25 there is provided an insulating film 14 for isolation which is formed by a polycrystalline silicon film for electrical isolation of an emitter lead-out electrode 18 and the base lead-out electrode 10 from each other. The emitter lead-out electrode 18 is provided so as to be connected to the main surface of the foregoing p-type base region 11 through an emitter opening 15.
The emitter lead-out electrode (polycrystalline silicon film) 18 of the bipolar transistor Bip having such double-polySi structure is formed along a stepped shape of the emitter opening 15. The stepped portion of the emitter opening 15 corresponds to the film thickness of the base lead-out electrode 9 and that of the insulating film 14, which electrically isolates the base lead-out electrode 9 from the emitter lead-out electrode 18. Since the polycrystalline silicon film emitter lead-out electrode 18 is deposited by CVD as noted previously, the film is almost uniform in thickness on both the flat portion and the stepped portion. More specifically, the polycrystalline silicon film 18 is formed so that the thickness thereof in the direction perpendicular to the semiconductor substrate 1 of the stepped portion around the emitter opening 15 is effectively larger than that of the central flat portion of the emitter opening 15. The concentration of n-type impurity (As) 17n which is introduced in the polycrystalline film around the emitter opening 15 is thus lower in the relatively thicker stepped portion than that of the central flat portion of the emitter opening in a position spaced a certain distance above the main surface of the p-type base region 11.
In other words, a peak position of the impurity concentration of the n-type impurity (As) 17n introduced in the stepped portion of the peripheral polycrystalline silicon film 18 is spaced from the main surface of the p-type base region 10 as compared with a peak position at the central flat portion of the emitter opening 15. Consequently, the amount of the n-type impurity (as) 17n diffused from the peripheral stepped portion to the main surface of the p-type base region 10 is smaller that of the n-type impurity (As) 17n diffused from the central flat portion of the polycrystalline silicon film that forms the emitter lead-out electrode 18 to the main surface of the p-type base region 10, so that the diffusion distance of the n-type impurity (As) 17n becomes longer. More specifically, as is apparent from FIG. 25, diffusion paths b and c of the n-type impurity 17n introduced in the peripheral polycrystalline silicon film are longer than a diffusion path a of the n-type impurity 17n introduced in the central polycrystalline film of the emitter opening 15. Therefore, at the main surface of the p-type region 10, the n-type impurity (As) 17n is not diffused up to the outer periphery of the emitter opening 15, and even when it is diffused in the main surface of the p-type base region 10, it is impossible to obtain an impurity concentration sufficient to invert the conductivity type of the p-type base region 10. Consequently, even if the n-type emitter region 17 is formed in the region defined by the emitter opening 15, the p-type base region 10 is present around the emitter region 17 in the emitter opening 15, so there has been the problem that the emitter lead-out electrode 18 and the p-type base region 10 are short-circuited in regions d shown in FIG. 25. This short-circuit decreases the yield in the manufacture of the semiconductor integrated circuit device and deteriorates the electrical reliability of the same device.
Such a problem is particularly conspicuous as the degree of integration increases. The size of the emitter opening, especially the emitter width, of the bipolar transistor tends to be reduced in accordance with the proportional reduction rule, but the polycrystalline silicon film emitter lead-out electrode 18 tends to become relatively thicker, contrary to the proportional reduction rule. It is necessary to ensure at least about 100 to about 150 nm as the thickness of the emitter electrode polycrystalline silicon film to prevent the penetration to the p-type base region 10 of n-type impurity which is introduced by ion implantation, to prevent the penetration to alloy pits by an aluminum electrode formed in the subsequent manufacturing step, and to reduce the amount of the film scraped off during washing and the amount of film consumed as silicide.
The foregoing short-circuit problem can be overcome by lengthening the diffusion distance of the n-type impurity for the formation of the emitter region, which is attained by increasing the heat treatment temperature and duration in the drive-in diffusion method. However, such high temperature and long heat treatment time create a problem in that the junction depth of the emitter region becomes large, and it is impossible to attain a high frequency characteristic or a high degree of integration of the bipolar transistor.
It is an object of the present invention to provide a technique capable of improving the yield in the manufacture of a semiconductor integrated circuit device having a self-aligned bipolar transistor.
It is another object of the present invention to provide a technique capable of improving the electrical reliability of the semiconductor integrated circuit device.
It is a further object of the present invention to provide a technique capable of improving a high frequency characteristic or the degree of integration of the semiconductor integrated circuit device.
The objects and novel features of the present invention will become more apparent from the following description and the accompanying drawings.